. While broad adoption is still on the horizon, meeting time-to-market demands is going to require chipset makers, network vendors and original design manufacturers completely rethink silicon test workflows. Importantly, they’ll need to simultaneously streamline innovation, cut costs and reduce cycles.
The National Institute of Standards and Technology estimates that the cost of discovering defects after release may be up to 30 times more expensive than making these discoveries earlier in the design phase. And that’s just the tip of the iceberg for how budgets and development timelines spin out of control when dated test strategies get in the way.
As 5G, SD-WAN, IoT, edge cloud and more angle for critical time-to-market gains, new silicon testing processes will eventually power these efforts. The early numbers are in and they represent the promise of a fundamental shift as inefficient strategies give way to a new approach based on continuous pre and post-silicon testing.
Read on as we explore why pre-silicon verification and post-silicon validation has become so complex and initiatives underway to power innovation by fast-tracking time-consuming and costly processes.
The silicon DevOps juggling act
The silicon development cycle being tolerated by today’s stakeholders is a story of frustrating back-and-forths between design teams and manufacturers. These processes play out across continents with long stretches of delays as bugs are baked into silicon, shipped, discovered weeks later, and sent back to the drawing board for course correction. Millions are spent, more than a dozen months typically pass and the approach is still not foolproof.
In other cases, minimal cycles are conducted in favor of post-silicon validation strategies that save time but increase risk of underlying problems post-launch.
There is no shortage of cautionary tales among chipset makers that saw brand reputation and bottom lines take a serious hit following discovery of a silicon bug in a highly-adopted product. The impact of COVID-19 has only exacerbated these challenges.
Putting chipset design and manufacturing on simultaneous paths
The way forward is clear. To accelerate delivery, achieve testing efficiency and promote significant cost savings, it’s time to standardize on an approach that discovers bugs as they’re introduced and wipe them out before they ever make it to the silicon.
The shining star of this strategy is complete silicon emulation at the Layer 1 level, and eventually, beyond. When a chipset’s entire design can be emulated, testing and bug fixes can happen in real-time. Suddenly, months are shaved off a process that typically took a year or more to complete.
We’ve seen the results firsthand. Chipset vendors have gone from seven test cases per day to ten per hour. From 40 test hours per week to 168.
Beyond the many business benefits already discussed in this post, chipset makers also win with a simplified testbed powered by automation. Testing teams don’t need to learn different scripts or write millions of lines of code. Through automation, they can accelerate traditional testing cycles at every turn. We’ve seen the results firsthand. Chipset vendors have gone from seven test cases per day to ten per hour. From 40 test hours per week to 168. From regression cycles that lasted weeks to just days.
Though chipset makers recognize the value of testing early and invest accordingly, the strategy suggested here requires an entire testing ecosystem come together in pursuit of a better approach. One that includes pre- and post-silicon validation of physical or virtualized infrastructure and fully automated testbeds to maintain CI/CD integrity. On this front, Spirent is engaging key stakeholders to make end-to-end silicon testing, support and services a reality. This is an important step toward transforming business objectives into faster revenue cycles. And making it possible to focus on core competencies and first-to-market differentiators like reliability and continuous high performance.
, we’ll talk about how this new approach to testing works at a technical level. In the meantime, for a deep dive on how an evolved strategy may benefit your silicon testing processes.